1. Field of the Invention
This invention relates to an electrically rewritable semiconductor memory device, especially to a non-volatile semiconductor memory in which a data write operation into a bank and a data read operation from another bank are concurrently accessible.
2. Description of Related Art
EEPROMs are configured to have electrically rewritable non-volatile memory cells. Recently, in such the EEPROMs, an automatically executing function for data rewriting is installed.
Based on the automatically executing function, input an address and data together with a write command, and a data write cycle is automatically performed for cells in selected memory area with periodical write pulse applications and verify reads.
On the other hand, it is required for the EEPROMs to take a long time for data rewriting in comparison with data read. Therefore, once a data rewrite operation is started, it is necessary for taking a long waiting period until the following data read operation becomes possible. Recently, in order to shorten such the waiting period, a simultaneous access or a “concurrent access” function is installed in an EEPROM with simultaneously accessible and plural memory areas such that a data write operation into a bank and a data read operation for another bank may be simultaneously performed.
In order to achieve such a simultaneous access function, for example, a bank address decoder as shown in FIG. 13 may be used. This is an example of an EEPROM chip with a capacity of 64 M byte in which the upper three address bits, A19-A21, in the entire address bits, A0-A21, are used for bank selecting. External address signals A19-A21 are latched by a signal CEB, which designates for automatically executing of a data rewrite operation, and then decoded to generate signals BUSY0-3 for determining a bank to be rewritten.
FIG. 14 shows an assignment of the external address bits, A19-A21, to four banks, BANK0-BANK3. This is such an example that these banks are formed to have capacities as follows: BANK0=BANK3=8 Mbyte; BANK1=BANK2=24 Mbyte. For example, when the upper bits, A19, A20 and A21, are “1”s, the determining signals become as follows: BUSY3=“H”; and BUSY0=BUSY1=BUSY2=“L”. As a result, the bank BANK3 is selected as a data rewriting one. Usually, the determining signals are output to outside of the chip as write busy signals for teaching that the selected bank is in a busy state. It is allowed for users to perform a data read operation with respect to any one of the banks BANK0, BANK1 and BANK2, busy signals of which are “L”s (i.e., BUSY0=BUSY1=BUSY2=“L”), in parallel with the data rewrite operation for the bank BANK3.
In the concurrent accessible EEPROM in the prior art, sizes of the respective banks and a relationship between the input address and a to-be-rewritten bank are fixed as explained by use of FIG. 14. Usually, a small capacitive bank will be used for storing program, code and the like, while a large capacitive bank will be used for storing image data and so on. However, the EEPROM, in which the bank configuration is fixed as above-described, is impossible to meet many kinds of user's demands.
It has already been proposed a concurrent accessible EEPROM the bank configuration and the bank size of which are changeable (see Japanese Patent Application laid open (kokai) 13-325795). This Patent Application teaches such a scheme that ROM circuits are proposed for variably setting the bank configuration for each of a plurality of cores arranged.